1. Field of the Invention
Generally, the present disclosure relates to the field of manufacturing of microstructures, such as integrated circuits, and, more particularly, to analysis techniques used for process monitoring and/or process control.
2. Description of the Related Art
In manufacturing microstructures, such as integrated circuits, micromechanical devices, opto-electronic components and the like, device features, such as circuit elements, are typically formed on an appropriate substrate by patterning the surface portions of one or more material layers previously formed on the substrate. Since the dimensions, i.e., the length, width and height, of individual features are steadily decreasing to enhance performance and improve cost-effectiveness, these dimensions have to be maintained within tightly set tolerances in order to guarantee the required functionality of the complete device. Usually, a large number of process steps have to be carried out for completing a microstructure, and, thus, the dimensions of the features during the various manufacturing stages have to be thoroughly monitored to maintain process control and to avoid further cost-intensive process steps owing to process tools that fail to meet the specifications in the various manufacturing stages.
For example, in sophisticated CMOS devices, a very large number of transistors, such as N-channel transistors and P-channel transistors, have to be formed in and above a semiconductor layer, wherein these transistor elements may comprise critical device features, such as gate electrodes and the like, which may have a critical dimension of approximately 50 nm and less in currently available products. In addition to steadily shrinking critical dimensions of the device features, new materials and process strategies may frequently have to be implemented in order to further enhance reliability, performance and cost-effectiveness. Generally, the manufacturing of sophisticated field effect transistors may require new technologies due to limitations increasingly encountered by conventional planar transistor structures based on a gate dielectric material in the form of silicon dioxide, silicon oxynitride and other “conventional” dielectric materials, since these materials may typically result in significantly increased leakage currents, thereby resulting in undue heat generation, which may not be compatible with requirements of many types of semiconductor devices. The limitations of well-established and well-approved dielectric materials in gate electrode structures have fueled new technology approaches, such as non-planar transistor configurations and/or sophisticated gate electrode structures. For instance, the scalability of planar transistor configurations may be significantly expanded by using complex gate electrode structures on the basis of high-k dielectric materials, which are to be understood as materials having a dielectric constant of 10.0 or higher, in combination with metal-containing electrode materials. Consequently, new materials, such as high-k dielectric materials and the like, may have to be implemented into the overall manufacturing flow, thereby requiring appropriate manufacturing techniques for depositing and patterning these materials. For this reason, also any new types of byproducts may be created during the processing of these materials, which may also require a thorough monitoring and investigation with respect to any interactions with other materials and manufacturing processes.
In still other approaches for enhancing transistor performance of complex integrated circuits, strain-inducing mechanisms may be implemented into the overall manufacturing flow for forming field effect transistors since a strained channel region of a silicon-based transistor may provide enhanced transistor performance due to a modified charge carrier mobility caused by the strained silicon-based material. For this purpose, strain-inducing semiconductor alloys, such as silicon/germanium, silicon/carbon and the like, may be incorporated into the active regions in a local manner, thereby selectively inducing a desired type of strain in individual transistor elements. Also in this case, sophisticated patterning and deposition techniques may be required which have to be applied within tightly set process tolerances in order to maintain overall device variability at a low level.
Similarly, after completing the circuit elements in the semiconductor material of complex integrated circuits, a contact level has to be formed, which may be considered as an interface between the circuit elements in the semiconductor material and a complex metallization system, which may be considered as a wiring network for connecting the individual transistor elements and other circuit elements in accordance with the required circuit function. Since, at least in some device regions, a very high density of individual circuit elements may have to be provided, the contact level may have to be formed on the basis of extremely complex deposition and patterning techniques in order to provide appropriate interlayer dielectric materials and patterning the same so as to form contact openings and filling the same with an appropriate metal-containing material. For example, the formation of contact openings in an interlayer dielectric material represents an extremely challenging manufacturing stage for very complex integrated circuits, which may, for instance, comprise densely packed memory areas and the like, since densely spaced contact openings with a high aspect ratio and with critical dimensions of approximately 100 nm and significantly less may have to be formed in a reliable and predictable manner. Consequently, the interaction of the different materials and processes may have a significant influence on the overall production yield in modern semiconductor facilities.
Moreover, typically, very complex metallization systems are required in modern semiconductor devices, wherein the complexity of the metallization system may reside in the fact that a plurality of metallization layers may have to be formed on top of each other, wherein complex material systems may also have to be provided in each of the metallization layers. For example, in modern integrated circuits including a very large number of circuit elements, typically, copper in combination with sophisticated dielectric materials, so-called low-k dielectric materials or ultra low-k (ULK) materials, may be used in order to reduce signal propagation delay in the metallization system. Due to copper's intrinsic characteristics, substantially not to form volatile etch byproducts on the basis of most of the well-established plasma assisted etch chemistries, typically a process technique is applied in which a dielectric material may first be patterned so as to receive corresponding openings, such as trenches and via openings, which are subsequently filled with the copper material by electro-chemical deposition techniques. However, due to the fact that copper may readily diffuse in silicon dioxide, silicon, a plurality of low-k dielectric materials and the like, a reliable confinement of the copper is required, since even minute amounts of copper diffusing to device regions, such as active regions of transistors, may result in a significant change of the overall device characteristics. For this reason, complex barrier material systems may be provided, for instance in the form of tantalum, tantalum nitride, ruthenium, titanium, titanium nitride and the like, which may provide a desired diffusion hindering effect and which may establish the mechanical and chemical integrity of the copper material. Moreover, although copper-based interconnect structures may have a significantly lower electrical resistivity compared to, for instance, aluminum, the reduced dimensions of the interconnect structures may nevertheless result in very high current densities, thereby also requiring strong interfaces between the copper material and the surrounding dielectric material that may have to be provided by the barrier material and corresponding cap materials in order to obtain the required performance with respect to electromigration. Consequently, in the complex manufacturing sequence for forming metallization layers, sensitive dielectric materials may have to be patterned based on appropriate plasma-assisted etch processes, thereby also creating a plurality of etch byproducts, which may have a significant effect on the further processing of the device.
It is well known that, in sophisticated plasma-assisted etch processes, a complex reactive process atmosphere has to be established, which not only includes reactive radicals formed on the basis of fluorine, chlorine and oxygen and the like, but also includes a plurality of molecular species, which may form polymers during the complex interaction of the various species contained in the reactive atmosphere. For example, by adding appropriate hydrogen and carbon-containing process gases, the degree of polymerization may be controlled so as to adjust the general etch behavior during the plasma-assisted process. The polymers may preferably deposit or accumulate at sidewalls of corresponding openings, thereby reducing the lateral etch rate, which may result in an efficient mechanism for controlling the sidewall angle of critical openings. As discussed above, in particular when forming the contact level or sophisticated metallization systems, openings, such as contact openings and via holes, may have to be formed with a high aspect ratio (depth/width) of 5 and significantly higher, wherein a lateral dimension of the openings may be 100 nm or even 50 nm and less in highly sophisticated semiconductor devices. Moreover, in some sophisticated approaches, the polymerization mechanism during the plasma-assisted etch process may even be taken advantage of in reducing the lateral dimension of critical openings, thereby extending the scalability of presently available lithography and etch techniques. That is, upon adding polymerizing gas components, a layer of polymer materials may be formed on sidewalls of critical openings, thereby increasingly forming a layer of polymer material, thereby effectively reducing the lateral width. Due to the complex reaction mechanism, however, a precise knowledge of the composition of the polymer materials and their chemical and physical characteristics may have to be obtained in order to efficiently assess the impact of the polymer material on the semiconductor device. For example, as previously explained, in complex metallization systems, very sensitive dielectric materials, typically provided in the form of low-k dielectrics and porous low-k dielectrics (ULK), are used, at least in critical metallization levels, wherein, however, any additional polymer material may significantly affect any subsequent processes and may also influence the finally obtained electrical performance of the metallization system. One important aspect in forming complex metallization systems is the deposition of an appropriate barrier material prior to depositing the actual fill metal, such as copper, since the barrier material has to provide sufficient adhesion and diffusion blocking capabilities, while at the same time this material may have to provide appropriate interface characteristics in terms of electromigration. Consequently, the presence of any polymer materials which may be generated during the previous complex etch process may significantly influence the deposition of the conductive barrier materials. Moreover, when performing efficient cleaning processes prior to depositing the metal material system, the interaction of the polymer materials with the cleaning chemistry may have to be known in advance in order to appropriately assess the resulting characteristics of the dielectric material. Furthermore, during the plasma-assisted etch processes, the sensitive dielectric materials may typically be damaged since dangling silicon bonds may be present at the exposed surface areas after the plasma-assisted etch process, which may subsequently efficiently react with other components, such as polymer residues and the like, wherein the final surface characteristics may significantly depend on the overall process conditions. Typically, water molecules and the like may adhere to the surface and may finally significantly modify the dielectric characteristics, which in turn may result in an increased dielectric constant of the metallization layer under consideration.
Hence, at various stages during the fabrication of complex semiconductor devices and microstructure devices, the monitoring of surface conditions after performing a complex patterning process on the basis of plasma-assisted etch recipes has become an important aspect. That is, material characteristics on patterned surface areas, such as the presence of polymer materials and etch residues, have to be thoroughly monitored in order to maintain the process output of the various manufacturing stages within the tightly set tolerances. For this reason, a plurality of complex inspection and analysis techniques have been developed in order to characterize the physical and chemical behavior of polymer materials and etch residues formed in patterned semiconductor devices. Since a direct access of the polymer and etch residues on the patterned surface of the semiconductor device may be difficult to achieve, frequently these materials are removed by chemical interaction, for instance by applying appropriate plasma atmospheres or wet chemical etch chemistries in order to analyze the fragments in the plasma atmosphere or in the wet chemical solution. In this case, however, the polymers and the etch residues have to chemically interact in some way with the plasma atmosphere or the wet chemical etch chemistry so that the corresponding analysis results may reflect the material characteristics after the reaction with the plasma or the wet chemistry. Consequently, these analysis techniques are less reliable with respect to providing authentic results of the polymer materials and etch residues, which have initially been formed in the semiconductor device upon forming the patterned surface thereof. Moreover, the “measurement” samples obtained by these conventional process strategies may not allow efficient application of advanced analysis techniques, such as AES (auger electron spectroscopy), SIMS (secondary ion mass spectroscopy), IR (infrared) spectroscopy and the like. Since many of these very efficient analysis techniques may require a specific sample preparation or may require at least specifically designed measurement conditions, which may not be efficiently established on the basis of a plasma or a chemical solution, the surface condition obtained after sophisticated plasma-assisted etch processes may not be efficiently monitored and controlled on the basis of presently available analysis techniques, in particular when surface topographies are considered in which critical dimensions of 50 nm and even less may be encountered.
The present disclosure is directed to various methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.